(1) Field of the Invention
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit utilizing a partially recessed shallow trench isolation (STI) scheme, in conjunction with a passivating, silicon nitride cap, to fabricate borderless contacts.
In sub-micron technology shallow trench isolation (STI) has become a standard means of isolation for semiconductor devices and has replaced other isolation methods, i.e., LOCOS (Localized Oxidation of Silicon) which require more valuable area. In the conventional shallow trench isolation process, trenches are formed in a semiconductor substrate between electrically active areas, i.e., MOSFET gates and source/drains, and electrically isolate MOSFET""s from each other. The trenches are filled with an insulating material, such as silicon oxide, to provide electrical insulation. Active devices, including MOSFET""s, transistors and resistors are fabricated into the semiconductor substrate in the xe2x80x9cactivexe2x80x9d regions with shallow trench isolation (STI), isolating the regions in between the active devices.
As transistor dimensions approached sub-micron, the conventional contact structures in use started to limit the device performance in several ways. First, it is difficult to minimize the contact resistance if the contact hole was is also of minimum size and problems with cleaning small contact holes become a concern. In addition, with defined conventional contacts, the area of the source/drain regions cannot be minimized because the contact hole has be aligned to these regions with a separate masking step, and a large xe2x80x9cextraxe2x80x9d area has to be allocated for possible misalignment. Furthermore, this larger xe2x80x9cextraxe2x80x9d area also results in increased source/drain-to-substrate junction capacitance, which impacts device speed. Borderless contacts or xe2x80x9cunframedxe2x80x9d contacts solve many of the micron and sub-micron MOSFET contact problems, easing both the device ground rule designs and easing the processing problems associated with conventional xe2x80x9cframedxe2x80x9d contacts. The borderless contact makes better use of the space and area over the source/drain region, as will be described in more detail. Borderless contacts are part of the advanced designs and processing associated with shallow trench isolation (STI).
(2) Description of Related Art
With conventional shallow trench isolation (STI) processes, it is a problem to form a borderless contact over the trench region. The borderless contact or xe2x80x9cunframedxe2x80x9d contact is a contact which overlies and exposes both the active and isolation regions of the semiconductor substrate, usually for the purpose of making contact to a diffusion region formed in the substrate. One problem of forming borderless contacts in combination with conventional shallow trench isolation (STI) involves the etching of the contact hole opening through interlevel layers of dielectrics, while at the same time, trying to avoid etching the dielectric material in trench. Oftentimes, the dielectrics are types of silicon oxide, both for the interlevel and trench fill material. Therefore, the trench filled oxide can be etched and damaged due to the contact hole etch. If the trench isolation material is etched back along the wall of the trench, deleterious effects can occur, i.e., leakage and shorting at the edge of the P/N junction, especially when this region becomes filled with a conducting material.
U.S. Pat. No. 5,807,784 entitled xe2x80x9cDevice Isolation Methods for a Semiconductor Devicexe2x80x9d granted Sep. 15, 1998 to Kim describes a method of forming a device isolation layer in semiconductor device comprising of a two step method of forming field oxide in shallow trench isolation (STI). The first step consists of implanting oxygen ions into the bottom of trench in the field region of a semiconductor substrate, and oxidizing the oxygen implanted region to form a field oxide layer. The second step consists of depositing insulation material to further fill the trench.
U.S. Pat. No. 5,807,490 entitled xe2x80x9cMETHOD OF FILLING SHALLOW TRENCHESxe2x80x9d granted Sep. 8, 1998 to Fiegl et al shows a method of isolation in silicon integrated circuit processing which overfills the trench by a fill margin and then deposits a temporary layer of polysilicon having a thickness less than the trench depth. A oxide layer is used as a polishing stop. Th e temporary layer is polished outside the trench, using a fill layer and polishing stop layer as polishing stops for chemical mechanical polish (CMP). The polishing stop layer is removed by CMP, together with the same thickness of fill planarity. The remaining temporary layer is stripped and a final touch up polish of the fill layer stops on the pad nitride.
U.S. Pat. No. 5,817,568 entitled xe2x80x9cMethod of Forming a Trench Isolation Regionxe2x80x9d granted Oct. 6, 1998 to Chao describes a method, using multi-trench formation techniques, to define the respective depths of trenches having different widths. The method includes forming a buffer oxide layer and polishing stop layer, in sequence, above a semiconductor substrate. Then, the buffer oxide layer, the polishing stop layer and the semiconductor substrate are defined to form at least one narrow trench. Thereafter, the buffer oxide layer, the polishing stop layer and the semiconductor substrate are again defined to form at least one wide trench. Next, a portion of the oxide layer and a portion of the polishing stop layer are removed to form a planarized surface. Finally, the polishing stop layer and the buffer oxide layer are removed.
U.S. Pat. No. 5,652,176 entitled xe2x80x9cMethod for Providing Trench Isolation and Borderless Contactxe2x80x9d granted Jul. 29, 1997 to Maniar et al describes a method of trench isolation which uses a trench liner comprised of aluminum nitride. Another similar patent is U.S. Pat. No. 5,677,231 entitled xe2x80x9cMethod for Providing Trench Isolationxe2x80x9d granted Oct. 14, 1997 to Maniar et al also shows shallow trench isolation (STI) and a borderless contact process with an aluminum nitride liner under the STI silicon oxide. During the formation of the contact opening, using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at the corner of the trench. By protecting the junction, subsequent formation of a conductive plug will not electrically short circuit the junction, and keeps diode leakage low.
U.S. Pat. No. 5,268,330 entitled xe2x80x9cProcess for Improving Shee Resistance of an Integrated Circuit Device Gatexe2x80x9d granted Dec. 7, 1993 to Givens et al describes a process involving shallow trench isolation (STI) and contact above P-N junctions that can be made to be borderless contacts. A passivating layer is deposited over an integrated circuit device, fabricated using silicidation. An insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above the gate. The portion of passivating layer above the gate is removed. A trench above the junctions is formed by removing insulation and using the passivating layer as an etch stop. Then a portion of the passivating layer is removed above the junction. The gate can be further silicided and opening above the gate and trench can be filled. The contacts above the junction can be borderless contacts.
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit utilizing a partially recessed shallow trench isolation (STI) scheme, in conjunction with a passivating, silicon nitride cap, to fabricate borderless contacts.
A more specific object of the present invention is to provide an improved method of forming borderless contacts in the fabrication of integrated circuits on semiconductor substrates, which are typically single crystal silicon. The initial processes involves conventional formation of a pad oxide layer, which is formed by thermally growing a silicon dioxide layer. A xe2x80x9chard maskxe2x80x9d layer of silicon nitride is then deposited. A shallow trench for shallow trench isolation (STI) is patterned, as well as, the layers of hard mask nitride and pad oxide, all using a reverse mask process. A shallow trench is etched followed by the deposition of a thick layer of silicon oxide. The thick oxide layer forms a slight dip in the surface over the trench caused by the trench filling process. The surface is planarized, polishing the thick oxide layer back by chemical mechanical polish (CMP), so as to be nearly planar with the hard mask nitride layer. The hard mask nitride layer acts as a polishing stop.
In a first embodiment of the present invention, the above and other objectives are realized by using a method of fabricating a partially recessed shallow trench isolation (STI) structure, as described by the following method. After the planarization of the trench described above, a partial silicon oxide etch back is initiated either by using a dry etch process, or a wet etch process. The end result of the partial etch back step is to etch the oxide in the trench back to approximately halfway to three-quarters of the way down into the trench. More details for the partial etch back process of this present invention can be found in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.
In a second embodiment of the present invention, the above and other objectives are realized by using a method of fabricating a borderless contact, which consists of silicon nitride cap protection layer on top of a partially recessed trench oxide. This passivating nitride cap is accomplished in this invention by the following method. After the partial etch back of the trench oxide mentioned above, and removal of the hard mask, only a partially recessed oxide remains in the shallow trench. At this step in the process, a key process step in this invention is the formation of a silicon nitride cap layer in the trench. Therefore, after the partial STI oxide etch back and hard mask removal, a thick layer of silicon nitride is deposited by either a low pressure chemical vapor deposition (LPCVD) system or by a high density plasma (HDP) system and is performed, in such a manner, as to form a seamless STI nitride trench fill. Following the thick LPCVD or HDP nitride cap deposition, the surface is planarized by chemical mechanical polish (CMP) and the polish back process is stopped above the plane of trench opening and above the pad oxide layer, stopping well within the nitride cap layer. Thus, the pad oxide layer continues to remains in place. Next, the nitride cap layer is shaped and formed by partially removing the nitride layer by etching back to just below the pad oxide level. The process of partially etching back the nitride layer, places the silicon nitride cap in final form over the partially recessed STI oxide, acting a protecting passivating layer.
In a third embodiment of the present invention, the above and other objectives are realized by using a method of fabricating a borderless or xe2x80x9cunframedxe2x80x9d contact to substrate diffusion regions by taking advantage of the nitride cap, which is self-aligned and acts a protective passivating layer. Utilizing the nitride cap in a partially recessed oxide process, this method of contact hole formation and alignment has several advantages that will be described. The key point is that the silicon nitride cap is self-aligned and acts as a protective passivation layer in the region of the diffusions and the edge of the shallow trench isolation. One key advantage to the nitride cap is it forms a borderless contact without reducing the polysilicon to polysilicon spacing, a key design advantage. In addition, the nitride cap protects the shallow trench isolation edge, near the edge of the junction, from both contact hole mis-alignment and also from the salicide formation process. The nitride cap also electrically insulates the trench isolation edges and minimizes field edge intensive electrical leakage.
Another object of the present invention is to provide an improved method of forming trench fill. The partially recessed oxide, in the twofold STI fill process, oxide then nitride, described earlier, helps to fill trenches with high aspect ratios and helps to eliminate the STI seams and voids.
Convention processing steps that are employed in this invention to fabricate devices are stated as follows. Prior to the tungsten contact or plug/stud formation, several standard processes are performed: (a) polysilicon deposition, doping, anneal and patterning to form ploy gates (not shown in Figs.), (b) titanium silicide formation processes, (c) USG undoped silicate glass formation processes, (d) SACVD BPSG, sub-atmospheric chemical vapor deposition of boro phosphosilicate glass formation processes, (e) PE TEOS plasma enhanced TEOS tetraethylortho silicate deposited oxide (not shown in Figs.) for planarization of the surface. Included are all the standard processes associated with providing these layers, which form an interlevel dielectric layer (ILD). Contact holes are defined and etched followed by CVD tungsten depositing. Tungsten plug/stud formation results, and misaligment of the contact holes is taken care of by the nitride cap in this invention, which is both protective and passivating.